1. Field of the Invention
The present invention relates generally to a direct storage access device of the type utilizing partial-response signaling and maximum-likelihood (PRLM) detection together with digital filtering. More particularly, the present invention relates to an apparatus and method for reducing the time required to acquire synchronization with an incoming data stream.
2. Description of Related Art
Computers often include auxiliary memory storage units, such as disk drives, having media upon which data can be stored and later retrieved. Disk drives include magnetic rotating disks typically having concentric, radially-spaced tracks arranged on the surface of each disk, with data sectors being recorded on each track. A signal pick-up head moves over the surface of each disk to read or write data on the tracks of that disk.
A portion of the data written on the disk is used to recover timing information when the data is later read. The recovery of this timing information is performed using a phase locked loop (PLL) so that the sampling of data can be properly timed.
There are typically two modes of disk drive operation, acquisition mode and tracking mode. During the acquisition mode, the precise timing for data sampling is determined. In this regard, the PLL performs frequency lock-in by adjusting its free-running frequency to match the frequency of the incoming data. Thereafter, a phase lock-in sequence is performed where the PLL controls the phase of the clock so that it aligns with the phase of the incoming data signal.
The sampled data includes a preamble. This preamble is typically periodic in nature and contains many transitions (i.e. it has a high content of timing information). The preamble is used to facilitate the synchronization of the PLL with the incoming data. Because the size of the preamble adversely impacts disk format efficiency, it is highly desirable to reduce its length. Although the acquisition time must be decreased to reduce the length of the preamble, any reduction in the acquisition time is ultimately limited by the latency of the PLL, with a higher latency resulting in a longer acquisition time.
In addition, a higher latency makes it more difficult to use the PLL under optimal conditions. FIG. 1a shows the stability region of such a system for different latency values as a function of two loop parameters: the gain of the integral path (INTGAIN) and the gain of the proportional path (PROPGAIN). FIG. 1b shows in greater detail the stability region of
FIG. 1a. FIG. 2a shows the acquisition time profile of a PLL system without latency. FIG. 2b shows the acquisition time profile of a PLL system with latency. The useful operating range of a PLL system with latency is much more restricted than a system without latency, making it more difficult to accommodate part to part variations. The settling time defines the acquisition time length required to reduce the PLL phase error to .+-.1 least significant bit (LSB).
Each of the elements of a PLL system has its own inherent latency. Therefore, to achieve a reduction in acquisition time, the latency of the PLL system must be reduced.
One technique used to reduce the latency of the PLL system is to bypass the finite impulse response (FIR) filter during the acquisition phase. An example of this particular technique is illustrated in U.S. Pat. No. 5,220,466.
The equalization provided by the FIR filter can be avoided during the acquisition phase because of the periodic nature of the preamble. By avoiding the use of the FIR filter during the acquisition phase, the latency of the PLL system can be diminished, thereby decreasing the overall acquisition time through the use of a shorter preamble. As a result, the disk format efficiency is increased.
Even when "aided" acquisition techniques are employed to reduce the "acquisition" time, one is still confronted by the problem of latency, which can still decrease the effectiveness of those techniques. By way of example, an auxiliary circuit may be employed as a zero phase restart to jump start the clock in an accurate phase alignment with the incoming data. However, the latency of the PLL system will degrade the effectiveness of this technique due to the presence of an unavoidable frequency offset between the clock and incoming data. As a slight improvement on this technique, the auxiliary circuit may be used in conjunction with the bypassing technique discussed above because the effectiveness of this circuit, as well as that of other "aided" acquisition techniques, is reduced by the latency of the PLL system due to the presence of the frequency offset between the clock and the incoming data signal.
In view of the foregoing, a technique for reducing the acquisition time is needed which minimizes the latency of the PLL system.